(1) Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a circuit for controlling a column part of the semiconductor memory device.
(2) Description of the Prior Art
In a typical semiconductor memory device, a write operation or a read operation is accomplished by first selecting the desired row line, that is, word line, and then selecting the desired column line, that is, bit line. This allows the selection of the memory cell located at the cross point of the selected row and column lines and a write or read operation occurs.
As is obvious from the above, write or read operations are achieved for the column and row lines not simultaneously, but sequential. In light of this sequentially operation, an address multiplex access method has been proposed, for example in U.S. Pat. No. 3,969,706, July 13, 1976, in the name of Robert James Proebsting et al, entitled "Dynamic Random Access Memory MISFET Integrated Circuit". According to the address multiplex access method, first a row address strobe signal is externally supplied to the memory to establish a row access mode. Next, a column address strobe signal is externally supplied to establish a column access mode. The column access mode starts when the column address strobe signal and a column address enable signal are both given. The column address enable signal is usually generated after processing is completed. The processing is started by receiving the row address strobe signal.
In this regard, the recent trend in semiconductor memory devices is toward very high speed read and write operations. That is, the write or read access time must be as short as possible. In the prior art, there is a disadvantage in that the above-mentioned memory access operation cannot be conducted at a very high speed. This is because it takes a relatively long time to produce the aforementioned column address enable signal.